A Novel Circuit Reduction Technique to Determine the Response of the On-chip Vlsi Rc Interconnect for Ramp Input Excitation
نویسندگان
چکیده
AbstractIn present day sub-micron technology, reduction of circuit complexity of on-chip VLSI interconnects is an important issue for the analysis and verification of integrated circuits. In this paper, we present an exact method to compute the analytic time-domain response for a RC circuit including coupling capacitors for ramp input excitation. Accuracy and efficiency of the method is shown for various examples.
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An Accurate Modeling of Delay and Slew Metrics for On-chip Vlsi Rc Interconnects for Ramp Inputs Using Burr’s Distribution Function
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